(1) Field of the Invention
The present invention relates to a method of fabricating a capacitor, and more particularly, to a method of fabricating a capacitor having large capacitor surface area on a minimum chip area in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. As the technology in the semiconductor industry grows, the physical geometry of the semiconductor devices shrink. While maintaining the required capacitance, it is desirable to form the capacitor on as small a chip area as possible, thus reducing cell size.
U.S. Pat. No. 5,942,787 to Gardner teaches a method of using polysilicon spacers as a mask for making very small polysilicon features. U.S. Pat. No. 5,912,492 to Chang et al shows a capacitor having spacers over a FOX. U.S. Pat. No. 5,909,621 to Hsia et al, U.S. Pat. No. 5,854,105 to Tseng, and U.S. Pat. No. 5,712,202 to Liaw et al show capacitor processes using spacers of various types. U.S. Pat. No. 5,595,928 to Lu et al shows a process for forming polysilicon pillar capacitors.